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this data sheet may be revised by subs equent versions ?2004 eon silicon solution, inc., www. e s s i . c o m . t w or modifications due to changes in technical specifications. 1 en29lv800a en29lv800a 8 megabit (1024k x 8-bit / 512k x 16-bit) flash memory boot sector flash memory , cmos 3.0 volt-only features ? single power supply operation - full voltage range: 2.7-3.6 volt read and write operations for battery-powered applications. - regulated voltage range: 3.0-3.6 volt read and write operations and for compatibility with high performance 3.3 volt microprocessors. ? manufactured on 0.18 m triple-metal double poly triple-well cmos flash technology ? high performance - a ccess t i mes as f a st as 55 ns ? low power consumption (typical values at 5 mhz) - 7 ma typical active read current - 15 ma typical program/erase current - 1 a typical standby current (standard access time to active mode) ? flexible sector architecture: - one 16-kbyte, two 8-kbyte, one 32-kbyte, and fifteen 64-kbyte sectors (byte mode) - one 8-kword, two 4-kword, one 16-kword and fifteen 32-kword sectors (word mode) ? sector protection: - hardware locking of sectors to prevent program or erase operations within individual sect ors additionally, tempor ary sector unprotect allows code changes in previously locked sect ors. ? high performance program/erase speed - byte/word program time: 8s typical - sector erase time: 500ms typical ? jedec standard embedded erase and program algorithms ? jedec standard data# polling and toggle bits feature ? single sector and chip erase ? sector unprotect mode ? erase suspend / resume modes: read or program another sector during erase suspend mode ? low vcc write inhibit < 2.5v ? minimum 1,000k endurance cycle ? package options - 48-pin tsop (type 1) - 48-ball 6mm x 8mm fbga ? commercial and industrial temperature range general description the en29lv800a is an 8-megabit, electrically erasable, read/write non-volatile flas h memory, organized as 1,048,576 bytes or 524,288 words. any byte can be programmed typically in 8s. the en29lv800a features 3.0v voltage read and write operation, with access time as fast as 55ns to eliminate the need for wait statements in high-performance microprocessor systems. the en29lv800a has separate output enable (oe#), chip enable (ce#), and write enable (we#) controls, which eliminate bus contention issues. this device is designed to allow either single sector or full chip erase operation, where eac h sector can be individually protected against program/erase operations or tem porarily unprotected to erase or program. the device can sustain a minimum of 1,000k program/erase cycles on each sector. rev. c, issue date: 2005/01 / 10
this data sheet may be revised by subs equent versions ?2004 eon silicon solution, inc., www. e s s i . c o m . t w or modifications due to changes in technical specifications. 2 en29lv800a connection diagrams a16 by te# vss dq15/a-1 dq7 dq14 dq6 dq13 dq5 dq12 dq4 vcc dq11 dq3 dq10 dq2 dq9 dq1 dq8 dq0 oe# vss ce# a0 a15 a14 a13 a12 a11 a10 a9 a8 nc nc we # reset# nc nc ry/ b y# a18 a17 a7 a6 a5 a4 a3 a2 a1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 sta nda rd tsop a6 a5 a4 a1 a3 a2 fb ga t o p v i ew , b a lls facin g do w n a1 3 a9 a3 ry / b y # we # a7 b6 b5 b4 b1 b3 b2 a1 2 a8 a4 n c r e s et# a1 7 c6 c5 c4 c1 c3 c2 a1 4 a1 0 a2 a1 8 n c a6 d6 d5 d4 d1 d3 d2 a1 5 a1 1 a1 n c n c a5 e6 e5 e4 e1 e3 e2 a1 6 dq7 a0 dq 2 dq 5 dq 0 f6 f5 f4 f3 f2 by t e # dq1 4 ce# dq1 0 dq1 2 dq8 g6 g5 g4 g3 g2 dq 15 / a - 1 dq1 3 oe # dq1 1 vc c dq9 h6 h5 h3 h2 vs s dq6 vs s dq 4 dq1 f1 g1 h4 h1 dq 3 rev. c, issue date: 2005/01 / 10
this data sheet may be revised by subs equent versions ?2004 eon silicon solution, inc., www. e s s i . c o m . t w or modifications due to changes in technical specifications. 3 en29lv800a table 1. pin description figure 1. logic diagram pin na me func tion a 0 - a 1 8 a d d r e s s e s dq0-dq14 15 data inputs/outputs dq15 / a-1 dq15 (data input/output, w o rd mode), a-1 (lsb address input, by te mode) c e # c h i p e n a b l e o e # o u t p u t e n a b l e reset # hardw a re reset pin r y / b y # r e a d y /busy o u t p u t w e # w r i t e e n a b l e vcc supply voltage (2.7-3.6v) v s s g r o u n d nc not connected to any thing byt e # b y te/w o r d m o d e en2 9lv 8 0 0a d q 0 ? d q 15 ( a - 1 ) a0 - a1 8 we# ce # ry / b y # res e t # byt e # oe # rev. c, issue date: 2005/01 / 10
this data sheet may be revised by subs equent versions ?2004 eon silicon solution, inc., www. e s s i . c o m . t w or modifications due to changes in technical specifications. 4 en29lv800a table 2a. top boot block sector architecture address range sec t or ( x 1 6 ) ( x 8 ) sect o r size (kby tes / kw ords) a 1 8 a 17 a 1 6 a 1 5 a 1 4 a 1 3 a 1 2 1 8 7 e 0 0 0 h - 7 f f f f h fc000h-fffffh 1 6 / 8 1 1 1 1 1 1 x 1 7 7 d 0 0 0 h - 7 d f f f h fa000h-fbfffh 8 / 4 1 1 1 1 1 0 1 1 6 7 c 0 0 0 h - 7 c f f f h f 8 0 0 0 h - f 9 f f f h 8 / 4 1 1 1 1 1 0 0 1 5 7 8 0 0 0 h - 7 b f f f h f0000h ? f7fffh 3 2 / 1 6 1 1 1 1 0 x x 14 70000h-77fffh e0000h - effffh 64/32 1 1 1 0 x x x 13 68000h-6ffffh d0000h - dffffh 64/32 1 1 0 1 x x x 12 60000h-6ffffh c0000h - cffffh 64/32 1 1 0 0 x x x 11 58000h-5ffffh b0000h - bffffh 64/32 1 0 1 1 x x x 10 50000h-57fffh a0000h - affffh 64/32 1 0 1 0 x x x 9 48000h-4ffffh 90000h - 9ffffh 64/32 1 0 0 1 x x x 8 40000h-47fffh 80000h - 8ffffh 64/32 1 0 0 0 x x x 7 38000h-3ffffh 70000h - 7ffffh 64/32 0 1 1 1 x x x 6 30000h-37fffh 60000h - 6ffffh 64/32 0 1 1 0 x x x 5 28000h-2ffffh 50000h ? 5ffffh 64/32 0 1 0 1 x x x 4 20000h-27fffh 40000h ? 4ffffh 6 4 / 3 2 0 1 0 0 x x x 3 18000h-1ffffh 30000h ? 3ffffh 64/32 0 0 1 1 x x x 2 10000h-17fffh 20000h - 2ffffh 64/32 0 0 1 0 x x x 1 08000h-0ffffh 10000h - 1ffffh 64/32 0 0 0 1 x x x 0 00000h-07fffh 00000h - 0ffffh 64/32 0 0 0 0 x x x rev. c, issue date: 2005/01 / 10
this data sheet may be revised by subs equent versions ?2004 eon silicon solution, inc., www. e s s i . c o m . t w or modifications due to changes in technical specifications. 5 en29lv800a table 2b. bottom boot block sector architecture address range sec t or ( x 1 6 ) ( x 8 ) sect o r size (kby tes/ kw ords) a 1 8 a 17 a 1 6 a 1 5 a 1 4 a 1 3 a 1 2 18 78000h-7ffffh f0000h ? fffffh 6 4 / 3 2 1 1 1 1 x x x 17 70000h-77fffh e0000h ? effffh 6 4 / 3 2 1 1 1 0 x x x 16 68000h-6ffffh d0000h ? dffffh 64/32 1 1 0 1 x x x 15 60000h-67fffh c0000h ? cffffh 6 4 / 3 2 1 1 0 0 x x x 14 58000h-5ffffh b0000h - bffffh 64/32 1 0 1 1 x x x 13 50000h-57fffh a0000h - affffh 64/32 1 0 1 0 x x x 12 48000h-4ffffh 90000h ? 9ffffh 6 4 / 3 2 1 0 0 1 x x x 11 40000h-47fffh 80000h ? 8ffffh 6 4 / 3 2 1 0 0 0 x x x 1 0 3 8 0 0 0 h - 3 f f f f h 70000h ? 7 f f f f h 6 4 / 3 2 0 1 1 1 x x x 9 30000h-37fffh 60000h ? 6ffffh 6 4 / 3 2 0 1 1 0 x x x 8 28000h-2ffffh 50000h ? 5ffffh 64/32 0 1 0 1 x x x 7 20000h-27fffh 40000h ? 4ffffh 6 4 / 3 2 0 1 0 0 x x x 6 18000h-1ffffh 30000h ? 3ffffh 64/32 0 0 1 1 x x x 5 10000h-17fffh 20000h ? 2ffffh 6 4 / 3 2 0 0 1 0 x x x 4 08000h-0ffffh 10000h ? 1ffffh 64/32 0 0 0 1 x x x 3 04000h-07fffh 08000h ? 0ffffh 3 2 / 1 6 0 0 0 0 1 x x 2 0 3 0 0 0 h - 0 3 f f f h 06000h ? 07fffh 8 / 4 0 0 0 0 0 1 1 1 0 2 0 0 0 h - 0 2 f f f h 04000h ? 05fffh 8 / 4 0 0 0 0 0 1 0 0 0 0 0 0 0 h - 0 1 f f f h 00000h ? 03fffh 1 6 / 8 0 0 0 0 0 0 x rev. c, issue date: 2005/01 / 10
this data sheet may be revised by subs equent versions ?2004 eon silicon solution, inc., www. e s s i . c o m . t w or modifications due to changes in technical specifications. 6 en29lv800a product selector guide product number en29lv800a regulated voltage range: vcc= 3.0 ? 3.6 v -55r speed option f u ll voltage range: vcc= 2.7 ? 3.6 v - 7 0 - 9 0 max access t i me, ns ( t acc ) 5 5 7 0 9 0 max ce# access, ns ( t ce ) 5 5 7 0 9 0 max oe# access, ns ( t oe ) 3 0 3 0 3 5 block diagram we # ce# oe# sta t e c ont r o l co m m and r e gi st er eras e v o lta g e g e n e ra to r i n p u t / o ut pu t b u f f e r s p r og ram v o ltag e ge n e r a t o r ch ip en a b le o u tp u t e n a b le lo gi c dat a l a t c h y-d e co d e r x- d e c o de r y - ga tin g cell ma trix ti m e r v c c dete ctor a0 - a 1 8 vc c vs s d q 0- d q 15 (a - 1 ) a ddr e s s l a t c h b l oc k p r ot e c t sw i t c he s st b st b ry /by # rev. c, issue date: 2005/01 / 10
this data sheet may be revised by subs equent versions ?2004 eon silicon solution, inc., www. e s s i . c o m . t w or modifications due to changes in technical specifications. 7 en29lv800a table 3. operating modes 8m flash user mode table dq8-dq15 o p e r a t i o n c e # o e # w e # r e s e t # a0- a 1 8 d q 0 - d q 7 by te# = v ih by te# = v il r e a d l l h h a in d out d out h i g h - z w r i t e l h l h a in d in d in h i g h - z cmos standby v cc 0.3v x x v cc 0.3v x high-z high-z high-z ttl standby h x x h x high-z high-z high-z output disable l h h h x high-z high-z high-z hardware reset x x x l x high-z high-z high-z temporary sector u n p r o t e c t x x x v id a in d in d in x notes: l=logic low = v il , h=logic high= v ih , v id =11 0.5v, x=don?t care (either l or h, but not floating! ), d in =data in, d out =data out, a in =address in table 4. device identifiction (autoselect codes) 8m flash manufacturer/device id table description mode ce # oe # w e# a18 to a12 a11 to a10 a9 2 a8 a7 a6 a5 to a2 a 1 a 0 d q 8 to dq15 dq7 to dq0 manufacturer id: eon l l h x x v id h 1 x l x l l x 1 c h w o r d l l h 2 2 h d a h device id (top boot block) by t e l l h x x v id x x l x l h x d a h w o r d l l h 2 2 h 5 b h device id (bottom boot block) by t e l l h x x v id x x l x l h x 5 b h x 01h (protec t ed) sector protection verification l l h s a x v id x x l x h l x 00h (unprotec t ed) note: 1. if a manufacturing id is read w i th a8=l, the chip w ill output a configuration code 7fh. a further manufacturing id must be read w i th a8=h. 2. a9 = vid is for hv a9 autoselect mode only . a9 must be vcc (cmos logic level) for command autoselect mode. rev. c, issue date: 2005/01 / 10
this data sheet may be revised by subs equent versions ?2004 eon silicon solution, inc., www. e s s i . c o m . t w or modifications due to changes in technical specifications. 8 en29lv800a user mode definitions word / by te configuration the signal set on the byte# pin controls whether the device data i/o pins dq15-dq0 operate in the byte or word configuration. when the byte# pin is set at logi c ?1?, then the device is in word configuration, dq15-dq0 are active and are controlled by ce# and oe#. on the other hand, if the byte# pin is set at logic ?0?, then the devic e is in byte configuration, and only data i/o pins dq0-dq7 are active and contro lled by ce# and oe#. the data i/o pins dq8- dq14 are tri-stated, and the dq15 pin is used as an input for the lsb (a-1) address function. standby mode the en29lv800a has a cmos-compatible standby mode, which reduces the current to < 1a (typical). it is placed in cmos-compat ible standby when the ce# pin is at v cc 0.5. reset# and byte# pin must also be at cmos input levels. the device also has a ttl-compatible standby mode, which reduces the maximum v cc c u rrent to < 1ma. it is plac ed in ttl-c ompatible s t andby when t h e ce# pin is at v ih . when in standby modes, the outputs ar e in a high-impedance state independent of the oe# input. read mode the device is automatically set to reading arra y data after device power-up. no commands are required to retrieve data. the device is also ready to read array data after completing an embedded program or embedded erase algorithm. after the device accepts an erase suspend comm and, the device enters the erase suspend mode. the system can read array data using the standard read timings, except that if it reads at an address within erase-suspended sectors, the device output s status data. after completing a programming operation in the erase suspend mode, the system may once again read array data with the same exception. see ?erase suspend/erase resume commands? for more additional information. the system must issue the reset command to re -enable the device for reading array data if dq5 goes high, or while in the autoselect mode. see the ?reset command? additional details. output disable mode when the oe# pin is at a logic high level (v ih ), the output from the en 29lv800a is disabled. the output pins are placed in a high impedance state. auto select identification mode the autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on dq15?dq0. this mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. however, the autoselect c odes can also be accessed in-system through the command register. when using programming equipment, the autoselect mode requires v id (10.5 v to 11.5 v) on address pin a9. address pins a8, a6, a1, and a0 must be as shown in autoselect codes table. in addition, when verifying sector protection, t he sector address must appear on the appropriate highest order address bits. refer to the corresponding sector address tables. the command definitions table shows the remaining address bits that are don?t-care. when all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on dq15?dq0. rev. c, issue date: 2005/01 / 10
this data sheet may be revised by subs equent versions ?2004 eon silicon solution, inc., www. e s s i . c o m . t w or modifications due to changes in technical specifications. 9 en29lv800a to access the autoselect codes in-system; the host system can issue the autoselect command via the command register, as shown in the command de finitions table. this method does not require v id . see ?command definitions? for details on using the autoselect mode. write mode write operations, including programming data and er asing sectors of memory, require the host system to write a command or command sequence to the device. write cycl es are initiated by placing the byte or word address on the device?s addr ess inputs while the data to be written is input on dq[7:0] in byte mode (byte# = l) or on dq[15: 0] in word mode (byte# = h). the host system must drive the ce# and we# pins low and the oe# pin high for a valid write operation to take place. all addresses are latched on the falling edge of we# and ce#, whichever happens later. all data is latched on the rising edge of we# or ce#, whichever happens first. the system is not required to provide further controls or timings. the device aut omatically provides internally generated program / erase pulses and verifies the programmed /eras ed cells? margin. the host system can detect completion of a program or erase operation by obs erving the ry/by# pin, or by reading the dq[7] (data# polling) and dq[6] (toggle) status bits. the ?command definitions? section of this docum ent provides details on the specific device commands implemented in the en29lv800a. sector protection/unprotection the hardware sector protection feature disables both program and erase operations in any sector. the hardware sector unprotection feature re- enables both program and erase operations in previously protected sectors. there are two methods to enabling this hardware pr otection circuitry. the first one requires only that the reset# pin be at v id and then standard microprocessor timings can be used to enable or disable this feature. see flowchart 7a and 7b for the algorithm and figure 12 for the timings. when doing sector unprotect, all the ot her sectors should be protected first. the second method is meant for programming equipment. this method requires v id be applied to both oe# and a9 pin and non-standard microprocessor ti mings are used. this method is described in a separate document called en29lv800a suppl ement, which can be obtained by contacting a representative of eon silicon solution, inc. temporary sector unprotect start reset#=v id ( n ote 1) perform erase or program operations reset#=v ih t e mporary sector unprotect completed ( note 2 ) this feature allows temporary unpr otection of previously protected sector groups to change data while in-system. the sector unprotect mode is activated by setting the reset# pin to v id . during this mode, formerly protected sectors can be programmed or erased by simply selecting the sector addresses. once is removed from the reset# pin, all the previous ly protec ted s e c t ors are protected again. see accompanying figure and timing diagrams for more details. not e s : 1. all protected se ctors unprotected. 2. prev iously protec ted sectors protected again. rev. c, issue date: 2005/01 / 10
this data sheet may be revised by subs equent versions ?2004 eon silicon solution, inc., www. e s s i . c o m . t w or modifications due to changes in technical specifications. 10 en29lv800a automatic sleep mode the automatic sleep mode minimizes flash device energy consumption. t he device automatically enables this mode when addresses remain stable for t acc + 30ns. the automatic sleep mode is independent of the ce#, we# and oe # control signals. standard addr ess access timings provide new data when addresses are changed. while in sleep mode, output is latched and always available to the system. icc 4 in the dc characteristics table represents the automatic sleep more current specification. hardware data protection the command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes as seen in the command definitions table. additionally, the following hardware data protection measures prev ent accidental erasure or programming, which might otherwise be caused by false system level signals during vcc power up and power down transitions, or from system noise. low v cc write inhibit when vcc is less than v lko , the device does not accept any write cycles. this protects data during vcc power up and power down. the command register and all internal program/erase circuits are disabled, and the device resets. subsequent wr ites are ignored until vcc is greater than v lko . the system must provide the proper si gnals to the control pins to prev ent unintentional writes when vcc is greater than v lko . write pulse ?glitch? protection noise pulses of less than 5 ns (typical) on oe#, ce# or we# do not initiate a write cycle. logical inhibit write cycles are inhibited by holding any one of oe# = v il , ce# = v ih , or we# = v ih . to initiate a write cycle, ce# and we# must be a logical zero while oe# is a logical one. if ce#, we#, and oe# are all logical zero (not recommended usage), it will be considered a read. pow e r-up write inhibit during power-up, the device automatically resets to read mode and locks out write cycles. even with ce# = v il , we# = v il and oe# = v ih , the device will not accept commands on the rising edge of we#. rev. c, issue date: 2005/01 / 10
this data sheet may be revised by subs equent versions ?2004 eon silicon solution, inc., www. e s s i . c o m . t w or modifications due to changes in technical specifications. 11 en29lv800a command definitions the operations of en29lv800a are selected by one or more commands written into the command register to perform read/reset memory, read id, read sector protection, program, sector erase, chip erase, erase suspend and erase resu me. commands are made up of data sequences written at specific addresses via the command r egister. the sequences for the specified operation are defined in the command definitions table (table 5). incorrect addresses, incorrect data values or improper sequences will re set the device to read mode. table 5. en29lv800a command definitions bu s cy cles 1 st cy cle 2 nd cy cle 3 rd cy cle 4 th cy cle 5 th cy cle 6 th cy cle command se que nc e cycles a ddr data a ddr data a ddr data a ddr data a ddr data a ddr data r e a d 1 r a r d res e t 1 x x x f 0 w o r d 5 5 5 2aa 5 5 5 000/ 100 7f / 1c manufacturer id by te 4 aaa aa 555 55 aaa 90 000/ 200 7f / 1c w o r d 5 5 5 2aa 5 5 5 x01 2 2 d a device id t op boot by te 4 aaa aa 555 55 aaa 90 x02 d a w o r d 5 5 5 2aa 5 5 5 x01 2 2 5 b device id bottom boot by te 4 aaa aa 555 55 aaa 90 x02 5 b xx00 w o r d 5 5 5 2aa 555 (sa) x02 xx01 00 autoselect sector protect verify by te 4 aaa aa 555 55 aaa 90 (sa) x04 01 w o r d 5 5 5 2aa 5 5 5 program by te 4 aaa aa 555 55 aaa a 0 p a p d w o r d 5 5 5 2aa 5 5 5 unlock by pass by te 3 aaa aa 555 55 aaa 20 unloc k b y pas s p r ogr am 2 xxx a 0 p a p d unloc k b y pas s res e t 2 xxx 90 xxx 00 w o r d 5 5 5 2aa 5 5 5 555 2 a a 555 chip erase by te 6 aaa aa 555 55 aaa 80 aaa aa 555 55 aaa 10 w o r d 5 5 5 2aa 5 5 5 555 2 a a sector erase by te 6 aaa aa 555 55 aaa 80 aaa aa 555 5 5 s a 3 0 er ase suspend 1 xxx b0 e r as e res u m e 1 xxx 30 address and data values indicated in hex ra = read address: address of the memory location to be read. this is a read cy cle. rd = read data: data read from location ra duri ng read operation. this is a read cy cle. pa = program address: address of the memory location to be programmed. x = don?t-care pd = program data: data to be programmed at location pa sa = sector address: address of the sect or to be erased or verified. address bits a18-a12 uniquely select any sector. reading array data the device is automatically set to reading array dat a after power up. no commands are required to retrieve data. the device is also ready to read array data after completing an embedded program or embedded erase algorithm. following an erase suspend command, erase sus pend mode is entered. the system can read array data using the standard read timings, with the onl y difference in that if it reads at an address within erase suspended sectors, the device outputs status data. after completing a programming rev. c, issue date: 2005/01 / 10
this data sheet may be revised by subs equent versions ?2004 eon silicon solution, inc., www. e s s i . c o m . t w or modifications due to changes in technical specifications. 12 en29lv800a operation in the erase suspend mode, the system may once again read array data with the same exception. the reset command must be issued to re-enable the device for reading array data if dq5 goes high, or while in the autoselect mode. see next section for details on reset. reset command writing the reset command to the device resets the device to reading array data. address bits are don?t-care for this command. the reset command may be written between the sequence cycles in an erase command sequence before erasing begins. this resets the device to reading array data. once erasure begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the sequence cycles in a pr ogram command sequence before programming begins. this resets the device to reading array data (a lso applies to programming in erase suspend mode). once programming begins, however, the device i gnores reset commands until the operation is c o mplete. the reset command may be written between t he sequence cycles in an autoselect command sequence. once in the autoselect mode, the rese t command must be written to return to reading array data (also applies to autos elect during erase suspend). if dq5 goes high during a program or erase operati on, writing the reset command returns the device to reading array data (also applies during erase suspend). autoselect command sequence the autoselect command sequence allows the host sy stem to access the manufacturer and devices codes, and determine whether or not a sector is pr otected. the command definitions table shows the address and data requirements. this is an alternative to the method that requires v id on address bit a9 and is intended for prom programmers. two unlock cycles followed by the autoselect co mmand initiate the autoselect command sequence. autoselect mode is then entered and the system may read at addresses shown in table 4 any number of times, without needing another command sequence. the system must write the reset command to exit the autoselect mode and return to reading array data. word / by te programming command the device may be programmed by byte or by word, depending on the state of the byte# pin. programming the en29lv800a is performed by using a four bus-cycle operation (two unlock write cycles followed by the program setup command and program data write cycle). when the program command is executed, no additional cpu controls or timings are necessary. an internal timer terminates the program operation automatically. address is latched on the falling edge of ce# or we#, whichever is last; data is latched on the ri sing edge of ce# or we#, whichever is first. programming status may be checked by sampling data on dq7 (data# polling) or on dq6 (toggle bit). when the program operation is successfully completed, the device returns to read mode and the user can read the data programmed to the devic e at that address. note that data can not be programmed from a 0 to a 1. only an erase operation can change a data from 0 to 1. when programming time limit is exceeded, dq5 will produce a logical ?1? and a reset command can return the device to read mode. rev. c, issue date: 2005/01 / 10
this data sheet may be revised by subs equent versions ?2004 eon silicon solution, inc., www. e s s i . c o m . t w or modifications due to changes in technical specifications. 13 en29lv800a unlock by pass to speed up programming operation, the unlock bypa ss command may be used. once this feature is activated, the shorter two cycle unlock bypass program command can be used instead of the normal four-cycle program command to program the device. this mode is exited after issuing the unlock bypass reset command. the device powers up with this feature disabled. chip erase command chip erase is a six-bus-cycle operation. the ch ip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the embedded erase algorithm. the device does not require the system to preprogram prior to erase. the embedded erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings during these operations. the command definitions table shows the address and data requirements for the chip erase command sequence. any commands written to the chip during t he embedded chip erase algorithm are ignored. the system can determine the status of the erase operation by using dq7, dq6, or dq2. see ?write operation status? for information on these st atus bits. when the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. flowchart 4 illustrates the algorithm for the eras e operation. see the erase/program operations tables in ?ac characteristics? for parameters, and to the chip/sector erase operation timings for timing waveforms . sector erase command sequence sector erase is a six bus cycle operation. t he sector erase command sequence is initiated by writing two un-lock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the address of the sector to be erased, and the sector erase command. the command definitions table shows the address and data requirements for the sector erase command sequence. once the sector erase operation has begun, only the erase suspend command is valid. all other commands are ignored. when the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. the system can det ermine the status of the erase operation by using dq7, dq6, or dq2. refer to ?write operat ion status? for information on these status bits. flowchart 4 illustrates the algorithm for the erase operation. refer to the erase/program operations tables in the ?ac characteristics? section for parameters, and to t he sector erase operations timing diagram for timing waveforms. erase suspend / resume command the erase suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not se lected for erasure. this command is valid only during the sector erase operation. the erase sus pend command is ignored if written during the chip erase operation or embedded program algorithm. addresses are don?t-cares when writing the erase suspend command. when the erase suspend command is written during a sector erase operation, the device requires a maximum of 20 s to suspend the erase operation. rev. c, issue date: 2005/01 / 10
this data sheet may be revised by subs equent versions ?2004 eon silicon solution, inc., www. e s s i . c o m . t w or modifications due to changes in technical specifications. 14 en29lv800a after the erase operation has been suspended, the sy stem can read array data from or program data to any sector not selected for erasure. (t he device ?erase suspends? all sectors selected for erasure.) normal read and write timings and co mmand definitions apply. reading at any address within erase-suspended sectors produces status data on dq7?dq0. the system can use dq7, or dq6 and dq2 together, to determine if a sector is actively erasing or is erase-suspended. see ?write operation status? for info rmation on these status bits. after an erase-suspended program operation is co mplete, the system can once again read array data within non-suspended sectors. the system can determine the status of the program operation using the dq7 or dq6 status bits, just as in the standard program operati on. see ?write operation status? for more information. the autosele ct command is not supported during erase suspend mode. the system must write the erase resume command (address bits are don?t-care) to exit the erase suspend mode and continue the sector erase operation. further writes of the resume command are ignored. another erase suspend command can be wri tten after the device has resumed erasing. write operation status dq7: data# polling the en29lv800a provides data# polling on dq7 to indicate the status of the embedded operations. the data# polling feature is active during the embedded programming, sector erase, chip erase, and erase suspend. (see table 6) when the embedded programming is in progress, an attempt to read the device will produce the complement of the data last written to dq7. upon the completion of the embedded programming, an attempt to read the device will produce t he true data written to dq7. for the embedded programming, data# polling is valid after the risi ng edge of the fourth we# or ce# pulse in the four-cycle sequence. when the embedded erase is in progress, an attemp t to read the device will produce a ?0? at the dq7 output. upon the completion of the embedded eras e, the device will produce the ?1? at the dq7 output during the read cycles. for chip erase, the data# polling is valid after the rising edge of the sixth we# or ce# pulse in the si x-cycle sequence. data# polling is va lid after the last rising edge of the we# or ce# pulse for chip erase or sector erase. data# polling must be performed at any address wi thin a sector that is being programmed or erased and not a protected sector. otherwise, data# polling may give an inaccurate result if the address used is in a protected sector. just prior to the completion of the embedded operations, dq7 may change asynchronously when the output enable (oe#) is low. this means that t he device is driving status information on dq7 at one instant of time and valid data at the next instant of time. depending on when the system samples the dq7 output, it may read the status of valid data. even if the device has completed the embedded operations and dq7 has a valid data, the data output on dq0-dq6 may be still invalid. the valid data on dq0-dq7 will be read on the subsequent read attempts. the flowchart for data# polling (dq7) is shown on flowchart 5. the data# polling (dq7) timing diagram is shown in figure 8. ry/by#: ready / busy the ry/by# is a dedicated, open-drain output pin that indicates whether an embedded algorithm is in progress or completed. the ry/by# status is valid after the rising edge of the final we# pulse in rev. c, issue date: 2005/01 / 10
this data sheet may be revised by subs equent versions ?2004 eon silicon solution, inc., www. e s s i . c o m . t w or modifications due to changes in technical specifications. 15 en29lv800a the command sequence. since ry/by# is an open-dr ain output, several ry/by# pins can be tied together in parallel with a pull-up resistor to vcc. in the output-low period, signifying busy, the dev ice is actively erasi ng or programming. this includes programming in the erase suspend mode. if the output is high, si gnifying the ready, the device is ready to read array data (including duri ng the erase suspend mode), or is in the standby mode. dq6: toggle bit i the en29lv800a provides a ?toggle bit? on dq6 to i ndicate to the host syst em the status of the embedded programming and erase operations. (see table 6) during an embedded program or erase operation, succe ssive attempts to read data from the device at any address (by active oe# or ce#) will resu lt in dq6 toggling between ?zero? and ?one?. once the embedded program or erase operation is comple ted, dq6 will stop toggling and valid data will be read on the next successive attempts. during embedded programming, the toggle bit is valid after the rising edge of the fourth we# pulse in t he four-cycle sequence. during erase operation, the toggle bit is valid after the rising edge of the sixt h we# pulse for sector erase or chip erase. in embedded programming, if the sector being written to is protected, dq6 will toggles for about 2 s, then stop toggling without the dat a in the sector having changed. in sector erase or chip erase, if all selected sectors are prot ected, dq6 will toggle for about 100 s. the chip will then return to the read mode without changing data in all protected sectors. the flowchart for the toggle bit (dq6) is shown in flowchart 6. the toggle bit timing diagram is shown in figure 9 . dq5: exceeded timing limits dq5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. under these conditions dq5 produces a ?1.? this is a failure condition that indicates the program or erase cycle was not successfully comple ted. since it is possible that dq5 can become a 1 when the device has successfully completed its operation and has returned to read mode, the user must check again to see if the dq6 is toggling after detecting a ?1? on dq5. the dq5 failure condition may appear if the system tries to program a ?1? to a location that is previously programmed to ?0.? only an erase operation can change a ?0? back to a ?1.? under this condition, the device halts the operation, and when the operation has ex ceeded the timing limits, dq5 produces a ?1.? under both these conditions, the system must issue the reset command to return the device to reading array data. dq3: sector erase timer after writing a sector erase command sequence, the output on dq3 can be used to determine whether or not an erase operation has begun. (the se ctor erase timer does not apply to the chip erase command.) when sector erase starts, dq3 swit ches from ?0? to ?1.? this device does not support multiple sector erase command sequences so it is not very meaningful since it immediately shows as a ?1? after the first 30h command. future devices may s upport this feature. dq2: erase toggle bit ii the ?toggle bit? on dq2, when used with dq6, indi cates whether a particular sector is actively erasing (that is, the embedded erase algorithm is in progress), or whether that sector is erase- suspended. toggle bit ii is valid after the risi ng edge of the final we# pulse in the command sequence. dq2 toggles when the system reads at addresses within those sectors that have been rev. c, issue date: 2005/01 / 10
this data sheet may be revised by subs equent versions ?2004 eon silicon solution, inc., www. e s s i . c o m . t w or modifications due to changes in technical specifications. 16 en29lv800a selected for erasure. (the system may use either oe# or ce# to control the read cycles.) but dq2 cannot distinguish whether the sector is acti vely erasing or is erase-suspended. dq6, by comparison, indicates whether the device is active ly erasing, or is in erase suspend, but cannot distinguish which sectors are selected for erasure. thus, both status bits are required for sector and mode information. refer to the following table to compare outputs for dq2 and dq6. flowchart 6 shows the toggle bit algorithm, and the se ction ?dq2: toggle bit? explains the algorithm. see also the ?dq6: toggle bit i? subsection. refer to the toggle bit timings figure for the toggle bit timing diagram. the dq2 vs. dq6 figure shows t he differences between dq2 and dq6 in graphical form. reading toggle bits dq6/dq2 refer to flowchart 6 for the following discussion. whenever the system initially begins reading toggle bit status, it must read dq7?dq0 at least tw ice in a row to determine whether a toggle bit is toggling. typically, a system would note and store the value of the toggl e bit after the first read. after the second read, the system woul d compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has complet ed the program or erase oper ation. the system can read array data on dq7?dq0 on the following read cycle. however, if after the initial two read cycles, the sy stem determines that the t oggle bit is still toggling, the system also should note whether the value of dq5 is high (see the section on dq5). if it is, the system should then determine again w hether the toggle bit is toggling, since the toggle bit may have stopped toggling just as dq5 went high. if the t oggle bit is no longer toggling, the device has successfully completed the program or erase operat ion. if it is still toggling, the device did not complete the operation successfully , and the system must write the reset command to return to reading array data. the remaining scenario is that the system initially determines that the toggle bit is toggling and dq5 has not gone high. the system may continue to monitor the toggle bit and dq5 through successive read cycles, determining the status as described in the previous paragraph. alternatively, it may choose to perform other system tasks. in this ca se, the system must star t at the beginning of the algorithm when it returns to determine the st atus of the operation (top of flowchart 6). write operation status o p e r a t i o n d q 7 d q 6 d q 5 d q 3 d q 2 ry/by # embedded program algorithm d q 7 # t o g g l e 0 n / a no toggle 0 standar d mode embedded erase algorithm 0 toggle 0 1 toggle 0 reading within erase suspended sector 1 no toggle 0 n / a t o g g l e 1 reading within non-erase suspended sector d a t a d a t a d a t a d a t a d a t a 1 erase suspend mode erase-suspend program dq7# toggle 0 n/a n/a 0 rev. c, issue date: 2005/01 / 10
this data sheet may be revised by subs equent versions ?2004 eon silicon solution, inc., www. e s s i . c o m . t w or modifications due to changes in technical specifications. 17 en29lv800a table 6. status register bits d q n a me logic le v e l de f i n i t i o n ?1? erase complete or erase sector in erase suspend ? 0 ? e r a s e o n - g o i n g dq7 program complete or data of non-erase sector during erase suspend 7 data# polling dq7# program on-going ?-1-0-1-0-1-0-1-? e rase or program on-going dq6 read during erase suspend 6 t oggle bit ?-1-1-1-1-1-1-1-? erase complete ?1? program or erase error 5 e r r o r bit ?0? program or erase on-going ?1? erase operation start 3 erase ti m e b i t ?0? erase timeout period on-going ?-1-0-1-0-1-0-1-? chip erase, sector erase or erase suspend on currently addressed sector. (w hen dq5= 1, erase error due to currently addressed sector. program during erase suspend on- going at current address 2 t oggle bit dq2 erase suspend read on non erase suspend sector notes: dq7 data# polling: indicates the p/e c status check during program or erase, and on completion before checking bits dq5 for program or erase success. dq6 toggle bit: remains at constant level w hen p/e oper ations are complete or erase suspend is acknow ledged. successive reads output complementary data on dq6 w h ile programming or erase operation are on-going. dq5 error bit: set to ?1? if failure in programming or erase dq3 sector erase command timeout bit: operation has st arted. only possible command is erase suspend (es). dq2 toggle bit: indicates the erase status and allow s identification of the erased sector. rev. c, issue date: 2005/01 / 10
this data sheet may be revised by subs equent versions ?2004 eon silicon solution, inc., www. e s s i . c o m . t w or modifications due to changes in technical specifications. 18 en29lv800a embedded algorithms flow chart 1. embedded program star t wr i t e p r o g r a m comm and sequence (show n b e l o w ) d a ta # po ll d e v i ce las t a ddre s s ? p r ogra m m i ng done in cr e m e n t ad d r e s s no yes ve r i fy d a ta ? flow chart 2. embedded program command sequence see the command definitions section for more information on w o rd mode. 2a a h / 55h 555h / a a h 555h / a 0 h pro g r am address / pro g ram dat a rev. c, issue date: 2005/01 / 10
this data sheet may be revised by subs equent versions ?2004 eon silicon solution, inc., www. e s s i . c o m . t w or modifications due to changes in technical specifications. 19 en29lv800a flow chart 3. embedded erase w r ite erase command sequence data poll from sy stem or t oggle bit successfully completed yes data =ffh? no erase done st art flow chart 4. embedded erase command sequence see the command definitions section for more information on w o rd mode. chip eras e sec t or eras e 2a ah/5 5 h 555h/ a ah 555h/ 8 0 h 2a ah/5 5 h 555h/ a ah 555h/ 1 0 h 555h / a ah 2a ah/5 5h 555h / 80h 555h / a ah 2a ah/5 5h sec t or ad dr es s / 3 0 h rev. c, issue date: 2005/01 / 10
this data sheet may be revised by subs equent versions ?2004 eon silicon solution, inc., www. e s s i . c o m . t w or modifications due to changes in technical specifications. 20 en29lv800a no no dq7 = data ? dq5 = 1? dq7 = data ? yes yes no yes re ad data star t re a d da t a (1 ) f a il pas s flow chart 5. data# polling algorithm notes: (1) this second read is necessary in case the first read was done at the exact instant when the status data was in transition. no ye s dq6 = to g g l e ? dq5 = 1 ? dq 6 = to g g l e ? no no ye s ye s re a d da t a t w i c e st ar t r ead d a t a t w i c e ( 2 ) fa i l pas s flow chart 6. toggle bit algorithm notes: (2) this second set of reads is necessary in case the first set of reads was done at the exact instant when the status data was in transition. rev. c, issue date: 2005/01 / 10
this data sheet may be revised by subs equent versions ?2004 eon silicon solution, inc., www. e s s i . c o m . t w or modifications due to changes in technical specifications. 21 en29lv800a flow chart 7a. in-sy s tem sector protect flow chart reset# = v id wait 1 s fi rs t w r i t e cy cle = 60h? no temporary sector unprotect mode ye s set up sector address sector protect: write 60h to sector addr w i th a6 = 0, a1 = 1, a0 = 0 wait 150 s verify sector protect: write 40h to sector address w i th a6 = 0, a1 = 1, a0 = 0 wait 0.4 s read from sector address w i th a6 = 0, a1 = 1, a0 data = 01h? no plscnt = 25? increment plscnt no device failed ye s protect another sector ? no yes sector protect complete wr ite r e set command remove v id from reset# ye s reset plscnt = 1 plscnt = 1 start sector protect algorithm rev. c, issue date: 2005/01 / 10
this data sheet may be revised by subs equent versions ?2004 eon silicon solution, inc., www. e s s i . c o m . t w or modifications due to changes in technical specifications. 22 en29lv800a flow chart 7b. in-sy s tem sector unprotect flow chart plscnt = 1 reset# = v id wait 1 s fi rs t w r i t e cy cle = 60h? no ye s no protect all sectors: the indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address (see diagram 7a.) ye s sector unprotect: write 60h to sector address w i th a6 = 1, a1 = 1, a0 = 0 set up first sector address all sector s protected? temporary sector unprotect mode start wait 0.4 s verify sector unprotect: write 40h to sector address w i th a6 = 1, a1 = 1, a0 =0 read from sector address w i th a6 = 1, a1 = 1, a0 = 0 set up next sector address no ye s ye s sector unprotect com p lete wr ite r e set command remove v id from reset# no last sector verified? data = 00h? wait 15 ms increment plscnt no plscnt = 1000? sector unprotect algorithm ye s device failed rev. c, issue date: 2005/01 / 10
this data sheet may be revised by subs equent versions ?2004 eon silicon solution, inc., www. e s s i . c o m . t w or modifications due to changes in technical specifications. 23 en29lv800a table 7. dc characteristics (t a = 0c to 70c or - 40c to 85c; v cc = 2.7-3.6v) sy m b o l p a ra me te r te s t conditions m i n ty p m a x u n i t i li i nput leakage current 0v v in vcc 5 a i lo out put leakage current 0v v out vcc 5 a supply current (read) t t l 8 16 ma (read) cmos by t e 6 18 ma i cc1 (read) cmos word ce# = v il ; oe# = v ih ; f = 5 m h z 7 2 0 m a supply current (st andby - t t l ) ce# = v ih , byt e# = reset # = vcc 0. 3v (not e 1) 0 . 4 1. 0 m a i cc2 supply current (st andby - cmos) ce# = byt e# = reset # = vcc 0.3v (not e 1) 1 5. 0 a i cc3 supply current (program or erase) by t e program, sect or or chip erase in progress 1 5 3 0 m a i cc4 aut o mat i c sleep mode v ih = vcc 0. 3 v v il = vss 0. 3 v 1 5. 0 a v il i nput low volt age -0. 5 0. 8 v v ih i nput high volt age 0. 7 x vcc vcc 0. 3 v v ol out put low volt age i ol = 4. 0 ma 0. 4 5 v out put high volt age t t l i oh = -2 .0 ma 0. 85 x vcc v v oh out put high volt age cmos i oh = -100 a, vcc - 0. 4v v v id a9 volt age (elect ronic signat ure) 10. 5 11. 5 v i id a9 current (elect ronic signat ure) a9 = v id 1 0 0 a v lko supply volt age (erase and program lock-out ) 2. 3 2. 5 v notes 1. byte# pin can also be gnd 0.3v. byt e# and reset # pin input buffers are alw a y s enabled so that t hey draw pow er if not at f u ll cmos supply volt ages. rev. c, issue date: 2005/01 / 10
this data sheet may be revised by subs equent versions ?2004 eon silicon solution, inc., www. e s s i . c o m . t w or modifications due to changes in technical specifications. 24 en29lv800a test conditions 3.3 v device under t e st note: diodes are in3064 or equiv a lent 2.7 k ? 6.2 k ? c l test specifications test conditions -55r -70 -90 unit output load 1 ttl gate output load capacitance, c l 3 0 1 0 0 1 0 0 p f input rise and fall times 5 5 5 ns input pulse levels 0.0-3.0 0 .0-3.0 0.0-3.0 v input timing measurement reference levels 1 . 5 1 . 5 1 . 5 v output timing measurement reference levels 1 . 5 1 . 5 1 . 5 v rev. c, issue date: 2005/01 / 10
this data sheet may be revised by subs equent versions ?2004 eon silicon solution, inc., www. e s s i . c o m . t w or modifications due to changes in technical specifications. 25 en29lv800a ac characteristics hardw a re reset (reset#) speed options unit parameter std descript i on test setup - 5 5 r - 7 0 - 9 0 t ready reset# pin low to read or write embedded algorithms m a x 2 0 s t ready reset# pin low to read or write non embedded algorithms m a x 5 0 0 ns t rp reset# pulse width min 500 ns t rh reset# high time before read min 50 ns reset# timings ry /by # 0 v reset# ce# oe # t rp t rh t ready reset timings not during embbedded a l gorithms reset# ce# oe # ry /by # t rp t rh t ready reset timings during embedded a l gorithms rev. c, issue date: 2005/01 / 10
this data sheet may be revised by subs equent versions ?2004 eon silicon solution, inc., www. e s s i . c o m . t w or modifications due to changes in technical specifications. 26 en29lv800a ac characteristics word / by te configuration (by t e#) s p e e d u n i t std p a r a m e t e r d e s c r i p t i o n - 5 5 r - 7 0 - 9 0 t bcs byte# to ce# switching setup time min 0 0 0 ns t cbh ce# to byte# switching hold time min 0 0 0 ns t rbh ry/by# to byte# switching hold time min 0 0 0 ns byte# timings for read operations t bc s ce# oe# by t e# ce# we# t cb h t bc s by t e# t rb h ry/by# byte# timings for write operations not e : sw it ching byt e# pin not allow ed during embedded operat ions rev. c, issue date: 2005/01 / 10
this data sheet may be revised by subs equent versions ?2004 eon silicon solution, inc., www. e s s i . c o m . t w or modifications due to changes in technical specifications. 27 en29lv800a table 8. ac characteristics read-only operations characteristics parameter sy mbols sp eed op tio n s j e d e c s t a n d a r d descrip tio n t est setup - 5 5 r - 7 0 - 9 0 un it t avav t rc read cy cle t i me m i n 5 5 7 0 9 0 n s t avq v t acc address t o out put delay ce# = v il oe# = v il max 5 5 7 0 9 0 n s t elq v t ce chip enable t o out put delay oe# = v il max 5 5 7 0 9 0 n s t glqv t oe out put enable t o out put delay max 3 0 3 0 3 5 n s t ehq z t df chip enable t o out put high z max 1 5 2 0 2 0 n s t ghqz t df out put enable t o out put high z max 1 5 2 0 2 0 n s t axq x t oh ou tp u t h o ld t i me fro m addresses, ce# or oe#, w h ichever occurs f i rst m i n 0 0 0 n s notes: for ? 55r vcc = 3.0v 5% output load : 1 ttl gate and 30pf input rise and fall times: 5ns input rise levels: 0.0 v to vcc timing measurement reference level, input and output: 1.5 v for all others: vcc = 3.0v 5% output load: 1 ttl gate and 100 pf input rise and fall times: 5 ns input pulse levels: 0.0 v to vcc timing measurement reference level, input and output: 1.5 v addr esses ce# oe # we# outputs reset# ry /by # high z output valid addresses stable t df t oh t oeh t ce t oe t ac c t rc 0v figure 5. ac waveforms for read operations rev. c, issue date: 2005/01 / 10
this data sheet may be revised by subs equent versions ?2004 eon silicon solution, inc., www. e s s i . c o m . t w or modifications due to changes in technical specifications. 28 en29lv800a table 9. ac characteristics write (erase/program) operations parameter sy mbols sp eed op tio n s j e d e c s t a n d a r d descrip tio n - 5 5 r - 7 0 - 9 0 un i t t avav t wc writ e cy cle t i me m i n 5 5 7 0 9 0 n s t avwl t as address set up t i me m i n 0 0 0 n s t wlax t ah address hold t i me m i n 4 5 4 5 4 5 n s t dvwh t ds d a ta se tu p t i me m i n 2 5 3 0 4 5 n s t whdx t dh dat a hold t i me m i n 0 0 0 n s t oe s out put enable set up t i me m i n 0 0 0 n s read mi n 0 0 0 n s t oe h out put enable hold t i me t oggle and dat a # polling m i n 1 0 1 0 1 0 n s t ghw l t ghw l read recovery t i me bef ore writ e (oe# high t o we# low ) m i n 0 0 0 n s t elwl t cs ce# set upt ime min 0 0 0 ns t wheh t ch ce# hold t i me min 0 0 0 ns t wlwh t wp writ e pulse widt h m i n 3 0 3 5 4 5 n s t whdl t wph writ e pulse widt h high m i n 2 0 2 0 2 0 n s ty p 8 8 8 s t whwh1 t whwh1 programming operat ion (word and by t e mode) m a x 2 0 0 2 0 0 2 0 0 s t whwh2 t whwh2 sect or erase operat ion t y p 0 . 5 0. 5 0. 5 s t vcs vcc setup t i me m i n 5 0 5 0 5 0 s t vidr r i se t i me to v id min 5 0 0 5 0 0 5 0 0 ns rev. c, issue date: 2005/01 / 10
this data sheet may be revised by subs equent versions ?2004 eon silicon solution, inc., www. e s s i . c o m . t w or modifications due to changes in technical specifications. 29 en29lv800a table 10. ac characteristics write (erase/program) operations a l tern ate ce# controlle d write s parameter sy mbols sp eed op tio n s jedec standard descrip tio n - 5 5 r - 7 0 - 9 0 un i t t avav t wc writ e cy cle t i me m i n 5 5 7 0 9 0 n s t avel t as address set up t i me m i n 0 0 0 n s t elax t ah address hold t i me m i n 4 5 4 5 4 5 n s t dveh t ds d a ta se tu p t i me m i n 2 5 3 0 4 5 n s t ehdx t dh dat a hold t i me m i n 0 0 0 n s t oe s out put enable set up t i me m i n 0 0 0 n s read m i n 0 0 0 n s t oe h out put enable hold t i me t o g g l e a n d dat a# polling m i n 1 0 1 0 1 0 n s t ghe l t ghe l read recovery t i me bef ore writ e (oe# high t o ce# low ) m i n 0 0 0 n s t wlel t ws we# set upt ime m i n 0 0 0 n s t ehwh t wh we# hold t i me m i n 0 0 0 n s t eleh t cp writ e pulse widt h m i n 3 0 3 5 4 5 n s t ehel t cph writ e pulse widt h high m i n 2 0 2 0 2 0 n s t y p 8 8 8 s t whwh 1 t whwh1 programming operat ion (by t e and w o rd mode) m a x 2 0 0 2 0 0 2 0 0 s t whwh 2 t whwh2 sect or erase operat ion t y p 0 . 5 0. 5 0. 5 s t vcs vcc setup t i me m i n 5 0 5 0 5 0 s t vidr r i se t i me to v id min 5 0 0 5 0 0 5 0 0 ns rev. c, issue date: 2005/01 / 10
this data sheet may be revised by subs equent versions ?2004 eon silicon solution, inc., www. e s s i . c o m . t w or modifications due to changes in technical specifications. 30 en29lv800a table 11. erase and pr ogramming performance limits parameter ty p m a x u n i t comments sect or erase t i me 0. 5 10 sec chip erase t i me 8 sec excludes 00h programming prior t o erasure by t e programming t i me 8 300 s word programming t i me 8 300 s by t e 8 . 4 25. 2 chip programming ti m e w o r d 4 . 2 12. 6 sec excludes sy st em level overhead erase/ program endurance 100k cy cles minimum 100k cy cles table 12. latch up characteristics parameter descrip tio n min max i nput volt age w i t h respect t o v ss on all pins except i / o pins (including a9, reset and oe#) -1. 0 v 12. 0 v i nput volt age w i t h respect t o v ss on all i / o pins -1. 0 v vcc + 1. 0 v vcc current -100 ma 100 ma note : these are latch up characteristics and the device should never be put under these conditions. refer to absolute maximu m ratings for the actual operating limits. table 14. 48-pin tsop pin capacitance @ 25c, 1.0mhz parameter sy mb o l parameter descrip tio n t est setu p t y p max un it c in i nput capacit ance v in = 0 6 7 . 5 pf c out out put capacit ance v out = 0 8. 5 1 2 pf c in2 cont rol pin capacit ance v in = 0 7. 5 9 pf table 15. data retention parameter description test conditions min unit 1 5 0 c 1 0 y e a r s min i mu m pa tte rn d a ta r e te n t io n t i me 1 2 5 c 2 0 y e a r s rev. c, issue date: 2005/01 / 10
this data sheet may be revised by subs equent versions ?2004 eon silicon solution, inc., www. e s s i . c o m . t w or modifications due to changes in technical specifications. 31 en29lv800a ac characteristics figure 6. ac waveforms for chip/s ector erase operations timings erase command sequence (last 2 cy cles) r ead status data (last tw o cy cles) addr esses s t a t u s d out v a v a t wc t as t ah t rb t vcs t dh t ds t busy t wp h t ch t wp t cs t ghw l t wh wh 2 or t wh wh 3 0x 2 a a s a 0 x 5 5 0 x 3 0 0x 555 for chip erase ce# oe # we# data ry /by # v cc not e s: 1. sa= sect or address (f or sect or erase), va= valid address f o r reading st at us, d out = t rue dat a at read address. 2. v cc show n only to illustrate t vc s measurement ref e rences. i t cannot occur as show n during a valid command sequence. rev. c, issue date: 2005/01 / 10
this data sheet may be revised by subs equent versions ?2004 eon silicon solution, inc., www. e s s i . c o m . t w or modifications due to changes in technical specifications. 32 en29lv800a figure 7. program operation timings program command sequence (last 2 cy cles) program command sequence (last 2 cy cles) t wc t as t ah addr esses 0 x 5 5 5 p a p a p a ce# t ghw l oe # t wp t ch we# t wp h t wh wh 1 t cs data p d s t a t u s d out ox a0 t ds t rb busy t t dh ry /by # t vcs v cc not e s: 1. pa= program address, pd= p rogram dat a , d out is t he t r ue dat a at t he program address. 2. v cc show n in order to illustrate t vc s measurement ref e rences. i t cannot occur as show n during a valid command sequence. rev. c, issue date: 2005/01 / 10
this data sheet may be revised by subs equent versions ?2004 eon silicon solution, inc., www. e s s i . c o m . t w or modifications due to changes in technical specifications. 33 en29lv800a figure 8. ac waveforms for /data polling during embedded algorithm operations not e s : ry /by # dq[6:0] dq[7] we# oe # ce# addr esses va va va t rc t ch t acc t ce valid data valid data status dat a true true co m p le - ment status data complement t oe t b u s y t oh t df t oeh 1. va=valid address for r eading data# polling status data 2. this diagram show s the first status cy cle after the command sequence, the last status read cy cle and the array data read cy cle. figure 9. ac waveforms for toggl e bit during embedded algorithm operations (stops toggling) valid data valid status t acc t ce t oe t oeh t ch t df t oh t busy v a v a valid status valid status (first read) (second d) addr esses ce# oe # we# dq6, dq2 ry /by # v a v a t rc rev. c, issue date: 2005/01 / 10
this data sheet may be revised by subs equent versions ?2004 eon silicon solution, inc., www. e s s i . c o m . t w or modifications due to changes in technical specifications. 34 en29lv800a figure 10. alternate ce# controlled write operation timings pa f o r pr og r a m sa f o r sector er ase 0x 555 f o r c h i p er ase 0x 555 f o r pr og r a m 0x 2aa f o r er ase no tes: pa = address of t he memory locat i on t o be programmed. pd = dat a t o be programmed at by t e address. va = valid address f o r reading program or erase st at us d out = array dat a read at va show n above are t he last t w o cy cles of t he program or erase command sequence and t he last st at us read cy cle reset# show n to illustrate t rh measurement ref e rences. i t cannot occur as show n during a valid command sequence. figure 11. dq2 vs. dq6 dq2 we# dq6 enter embedded erase erase suspend enter erase suspend program erase res u me e r a s e e n t e r suspend read enter suspend program erase erase complet e erase suspend read va d out status t wc reset# ry /by # data ce# oe # we# addr esses t rh t as t ah t wh t cph t cp t dh t ds pd f o r pr og r a m 0x 30 f o r sector er ase 0x 10 f o r c h i p er ase 0x a0 for program t busy t cw hw h1 / t cw hw h2 / t cw hw h3 t ws t ghe l rev. c, issue date: 2005/01 / 10
this data sheet may be revised by subs equent versions ?2004 eon silicon solution, inc., www. e s s i . c o m . t w or modifications due to changes in technical specifications. 35 en29lv800a figure 12. sector protect /unprotect timing diagram v id sa, a6,a1,a0 reset # 0 v t vid r t vid r >1 s 0v ce# we# oe# vcc 6 0 h 6 0 h valid verify sect or prot ect / u nprot ect sector protect: 150 us sector un p rotect: 15 ms >0 .4 s 4 0 h s t at u s valid valid dat a no tes: use st andard microprocessor t i mings f o r t h is device f o r read and w r it e cy cles. f o r sect or prot ect , use a6= 0 , a1= 1 , a0= 0 . f o r sect or unprot ect , use a6= 1 , a1= 1 , a0= 0 . temporary sector unprotect speed option unit parameter std descript i o n - 5 5 r - 7 0 - 9 0 t vidr v id rise and fall time min 500 ns t rsp reset# setup time for temporary sector unprotect min 4 s figure 13. temporary sector unprotect timing diagram 0 or 3 v reset # ry/by# we# ce# 0 or 3 v v id t rs p t vid r t vid r rev. c, issue date: 2005/01 / 10
this data sheet may be revised by subs equent versions ?2004 eon silicon solution, inc., www. e s s i . c o m . t w or modifications due to changes in technical specifications. 36 en29lv800a figure 14. tsop 12mm x 20mm rev. c, issue date: 2005/01 / 10
this data sheet may be revised by subs equent versions ?2004 eon silicon solution, inc., www. e s s i . c o m . t w or modifications due to changes in technical specifications. 37 en29lv800a rev. c, issue date: 2005/01 / 10
this data sheet may be revised by subs equent versions ?2004 eon silicon solution, inc., www. e s s i . c o m . t w or modifications due to changes in technical specifications. 38 en29lv800a figure 15. fbga 6mm x 8mm rev. c, issue date: 2005/01 / 10
this data sheet may be revised by subs equent versions ?2004 eon silicon solution, inc., www. e s s i . c o m . t w or modifications due to changes in technical specifications. 39 en29lv800a absolute maximum ratings p a r a m e t e r v a l u e u n i t storage temperature -65 to +125 c plastic packages -65 to +125 c ambient temperature with power applied -55 to +125 c output short circuit current 1 2 0 0 m a a9, oe#, res e t# 2 -0.5 to + 11.5 v all other pins 3 -0.5 to vc c + 0.5 v voltage with respect to ground vc c -0.5 to + 4 .0 v not e s : 1. no more than one output s horted at a time. duration of the short circuit should not be gr eater than one second. 2. minimum dc input v o ltage on a9, oe#, reset# pins is ?0.5v. during v o ltage tr ansitions, a9, oe#, reset# pins may undershoot v ss to ?1.0v for periods of up to 50ns and to ?2.0v for periods of up to 20ns. see figure below . max i mum dc input v o ltage on a9, oe#, and reset# is 11.5v w h ich may ov ershoot to 12.5v for periods up to 20ns. 3. minimum dc v o ltage on input or i/o pins is ?0.5 v. during v o ltage transitions, inputs may undershoot v ss to ?1.0v for periods of up to 50ns and to ?2.0 v for periods of up to 20ns. see figure below . max i mum dc v o ltage on output and i/o pins is v cc + 0.5 v. during v o ltage transit ions, outputs may ov ershoot to v cc + 1.5 v for periods up to 20ns. see figure below . 4. stresses abov e the v a lues so menti oned abov e may cause permanent damage to the dev ice. these v a lues are for a stress rating only and do not imply that the dev ic e should be operated at conditions up to or abov e these v a lues. ex posure of the dev ice to the max i mum rating v a lues for ex tended periods of time may adv ersely affect the dev ice reliability . recommended operating ranges 1 p a r a m e t e r v a l u e u n i t ambient operating temperature commercial devices industrial devices 0 to 70 -40 to 85 c regulated: 3.0 to 3.6 operating supply voltage v cc full: 2.7 to 3.6 v 1. recommended operating ranges defi ne those limits betw een w h ic h the functionality of the dev ice is guaranteed. vc c +1. 5 v maximum negat ive overshoot wavef o rm maximum posit i ve overshoot wavef o rm rev. c, issue date: 2005/01 / 10
this data sheet may be revised by subs equent versions ?2004 eon silicon solution, inc., www. e s s i . c o m . t w or modifications due to changes in technical specifications. 40 en29lv800a ordering information en29lv800a t - 70 t c p pa cka ging content (blank) = convent ional p = p b f r e e tempera t ure ra nge c = c o m m e r c i a l ( 0 c to +7 0 c) i = i ndust r ial (-40 c to +8 5 c) pa cka ge t = 48-pin t s op b = 48-ball fine pitch ball grid array (fbga) 0 . 8 0 mm p i tch , 6 mm x 8mm package speed 55r = 55ns (regulat ed) 70 = 70ns 90 = 90ns boot code sector a rchitecture t = t o p s e c t o r b = b o t t o m s e c t o r ba se pa rt number en = eon silicon solution inc. 29lv = f l ash, 3v read program erase 800 = 8 megabit (1024k x 8 / 512k x 16) a = version ident if ier rev. c, issue date: 2005/01 / 10
this data sheet may be revised by subs equent versions ?2004 eon silicon solution, inc., www. e s s i . c o m . t w or modifications due to changes in technical specifications. 41 en29lv800a revisions list revision no d e s c r i p t i o n d a t e a preliminary draft 2003/12/29 b add fpga outline as figre 15. 2004/02/13 c 1. wording and symbol revision. 2. update eon logo 3. dimension n corrected on page 37. 2005/01/10 rev. c, issue date: 2005/01 / 10

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